1. Field
Embodiments discussed herein relate to a receiving circuit.
2. Description of Related Art
In a high-speed signal transmission, a clock signal is recovered from the received data at receiver side and the recovered clock signal is used to perform the “0” or “1” determination of data (Clock and Data Recovery, CDR). The phase of the recovered clock signal is adjusted by a feedback circuit such that the recovered clock signal and the received data are in a certain phase relationship. The clock signal and data recovery circuit generates an appropriate clock signal based on the received data as well as detects the received data based on the generated clock.
Related arts are disclosed in Japanese Laid-open Patent Publication No. 2008-11173, Japanese Laid-open Patent Publication No. 2006-33824, and Japanese Laid-open Patent Publication No. 2006-101268, etc.